It becomes economically inefficient for some devices to test every die on each wafer at the end of the front-end process. This is because complex electrical testing of each die consumes a lot of test time and resources with high associated costs that can add significantly to the final manufacturing cost. Several types of adaptive wafer sort (WS) methods based on test results, such as the real-time adaptive test algorithm or the parallel test, where multiple devices are tested in parallel, are employed. These adaptive WS methods, although reducing wafer testing time, still require all wafers to be loaded into the prober and tested.
For some high-yield products, WS could eventually be omitted entirely. Then the WS cost is eliminated while the final test (FT) cost increases due to the lower FT yield and the additional cost of failed products at assembly (ASSY). Moreover, without WS that can provide an accurate assessment of current die quality, Fab-induced yield issues may not be discovered until weeks after the wafer has completed its processing at wafer fab and is tested at FT. This long delay can prevent prompt feedback to the wafer fab needed for timely process correction, which means that all wafers produced during the corresponding time interval can be affected too.
Deep learning algorithms open up the possibility of incorporating data inference to adopt smart product routing. If yield excursions can be predicted for a given wafer population, then those wafers could be routed for complete testing. Conversely, if yield is predicted to be good, then that wafer population could skip some testing down the line. This method can reduce total cost and increase effective testing capacity, while quality monitoring is not compromised. Smart product routing is a real-time method that can make cost-effective decisions without human intervention. To implement yield prediction and smart product routing, the following four modules are needed.
Published in the March issue of Semiconductor Digest in 2023 and available here.